--Archivo: pipem.vhd
--Fecha de creación: 15/01/2011
--Última fecha de modificación: 04/02/2011
--Diseñador: Pedro Marquez.
--Diseño: pipem
--Propósito: Registro de 5 bits compuesto por flip-flops tipo D

library IEEE;
use IEEE.std_logic_1164.all;

ENTITY pipem IS
PORT (	A_in  : in STD_LOGIC;
		B_in  : in STD_LOGIC;
		C_in  : in STD_LOGIC;
		D_in  : in STD_LOGIC;
		E_in  : in STD_LOGIC;
		F_in  : in STD_LOGIC;
 		CLK   : in STD_LOGIC;
		A_out : out STD_LOGIC;
		B_out : out STD_LOGIC;
		C_out : out STD_LOGIC;
		D_out : out STD_LOGIC;
		E_out : out STD_LOGIC;
		F_out : out STD_LOGIC );
END pipem;

ARCHITECTURE structural OF pipem IS

	COMPONENT ffd
	PORT ( 	D   : in  std_logic;
    		E   : in  std_logic;
		CLK : in  std_logic;
		Q   : out std_logic );

	END COMPONENT;

signal A_signal  : std_logic;
signal B_signal  : std_logic;
signal C_signal  : std_logic;
signal D_signal  : std_logic;
signal E_signal  : std_logic;
signal F_signal  : std_logic;
	
begin

    ffdA : ffd port map(
      D      => A_in,
      E      => CLK,
      CLK     => CLK,
      Q  => A_signal 
    );

    ffdB : ffd port map(
      D      => B_in,
      E      => CLK,
      CLK     => CLK,
      Q  => B_signal
    );

    ffdC : ffd port map(
      D      => C_in,
      E      => CLK,
      CLK     => CLK,
      Q  => C_signal 
    );

    ffdD : ffd port map(
      D      => D_in,
      E      => CLK,
      CLK     => CLK,
      Q  => D_signal 
    );

    ffdE : ffd port map(
      D      => E_in,
      E      => CLK,
      CLK     => CLK,
      Q  => E_signal 
    );

    ffdF : ffd port map(
      D      => F_in,
      E      => CLK,
      CLK     => CLK,
      Q  => F_signal 
    );

	A_out <= A_signal;
	B_out <= B_signal;
	C_out <= C_signal;
	D_out <= D_signal;
	E_out <= E_signal;
	F_out <= F_signal;

END structural;


